tech
AI's next bottleneck: Why even the best chips made in the U.S. take a round trip to Taiwan
Nvidia has reserved the majority of TSMC’s most advanced packaging capacity. The lesser-known chipmaking step may become the next bottleneck for AI.
TL;DR
- Advanced packaging, a key step for AI chips, is mainly done in Asia, creating a potential bottleneck.
- Capacity for advanced packaging is in short supply, despite significant growth in demand.
- TSMC, a leader in packaging, is increasing its CoWoS technology capacity by 80% annually.
- Nvidia has secured a majority of TSMC's most advanced packaging capacity.
- Intel, while technologically competitive, primarily performs final packaging overseas, with limited advanced packaging in the U.S.
- Elon Musk is tapping Intel for custom chip packaging for his ambitious projects.
- The U.S. is investing in domestic chip manufacturing and packaging, with TSMC building plants in Arizona.
- Advanced packaging methods like 2.5D (CoWoS) and future 3D packaging are essential for increasing chip performance and efficiency, extending Moore's Law.
- The reliance on Asian packaging facilities leads to longer turnaround times for U.S.-made chips.
- The semiconductor industry is exploring new techniques like hybrid bonding and 3D packaging (Foveros Direct, SoIC) for future advancements.